SRAM Leakage-Power Optimization Framework: a System Level Approach
نویسندگان
چکیده
SRAM Leakage-Power Optimization Framework: a System Level Approach
منابع مشابه
Standby supply voltage minimization for deep sub-micron SRAM
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. ...
متن کاملDOE-ILP Assisted Conjugate-Gradient Optimization of High-κ/Metal-Gate Nano-CMOS SRAM
Low power consumption and stability in Static Random Access Memories (SRAMs) is essential for embedded multimedia and communication applications. This paper presents a novel design flow for power minimization of nano-CMOS SRAMs, while maintaining their stability. A 32 nm High-κ/Metal-Gate SRAM has been used as example circuit. The baseline SRAM circuit is subjected to power minimization using a...
متن کاملLeakage power reduction techniques of 45 nm static random access memory (SRAM) cells
As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic VDD, negative word lin...
متن کاملAccurate Leakage-Conscious Architecture-Level Power Estimation Models for On-Chip SRAM Memory Arrays
Perhaps reinforced by the notion of a Moore’s Law, technology scaling has provided the IC industry with an integration capacity of billions of transistors. As transistors keep shrinking in size, leakage power dissipation dramatically increases and gradually becomes a first-class design constraint in more and more designs. To provide higher performance at lower power and energy for micro-archite...
متن کاملModeling and Simulation of High Level Leakage Power Reduction Techniques for 7T SRAM Cell Design
In this paper, the process of 7T SRAM cell is analyzing and also exploring the circuit topologies, high level leakage power reduction techniques and cell parameters. The first segment contains the information about process of the 7T SRAM cell like write operation and read operation. Second segment of this paper characterize high level the leakage power reduction techniques, containing the infor...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2008